Synopsys, Inc. (NASDAQ: SNPS) recently announced significant progress in silicon-proven IP, AI-driven EDA flows, and system-level technology enablement across TSMC’s advanced process and packaging nodes. The collaboration covers TSMC’s 3nm and 2nm process families, as well as A16™ and A14 nodes featuring Super Power Rail (SPR) technology.
By integrating intelligent digital, analog and verification flows, advanced 3D Multi-Die design capabilities, and opto-electronic co-design capabilities, Synopsys enables developers to enhance the quality of multi-physics analysis results and shorten the chip-to-system development cycle, addressing the increasingly complex design requirements of AI and high-performance computing applications.
Michael Buehler-Garcia, Senior Vice President at Synopsys, stated: “TSMC’s leading process and packaging technologies are opening new frontiers in performance, bandwidth and energy efficiency for AI and autonomous systems. Through our deep collaboration, Synopsys delivers AI-powered design flows, advanced multi-physics signoff capabilities, and a comprehensive portfolio of silicon-proven interface and foundation IP. This empowers customers to accelerate innovation and achieve superior design quality.”
Aveek Sarkar, Head of Ecosystem & Alliance Management at TSMC, commented: “We work closely with ecosystem partners such as Synopsys under the Open Innovation Platform® (OIP) to continuously expand coverage across TSMC’s advanced process nodes and 3DFabric® technologies, meeting the fast-growing demand in artificial intelligence and high-performance computing. By combining Synopsys’ certified EDA solutions and IP portfolio with our innovative process and packaging advancements, we help customers push the limits of performance, integration and energy efficiency to deliver leading chip solutions for next-generation AI systems.”
Accelerating 3DFabric Advancement Through Integrated Optical, Electrical and Thermal Analysis & Signoff
To support the growing scale and complexity of Multi-Die designs, Synopsys and TSMC have further strengthened design enablement for TSMC’s 3DFabric portfolio, including TSMC-SoIC® and CoWoS® technologies supporting interposers up to 5.5x reticle size. As a unified platform spanning design exploration through signoff, Synopsys 3DIC Compiler boosts design productivity via automation and enables implementation based on TSMC 3DFabric technologies. It is also integrated with RedHawk-SC™, RedHawk-SC Electrothermal™ and Ansys HFSS™, delivering comprehensive multi-physics analysis covering thermal, power integrity and high-speed signal integrity.
Leveraging Synopsys RedHawk-SC™ for digital power integrity analysis, Totem™ for analog power integrity analysis, and HFSS-IC Pro for electromagnetic extraction, the collaboration between Synopsys and TSMC has expanded from the A16™ process to A14. Synopsys Totem-SC™ provides ultra-high capacity analog power integrity signoff for large-scale N2 process designs and embedded memory. Meanwhile, Synopsys PathFinder-SC™ extends multi-chip ESD signoff coverage to the N2 node. Cloud-based multi-processing and GPU acceleration further shorten turnaround time, enabling fast iteration for multi-physics design teams working within complex thermally constrained 3D packaging structures.
The expanded multi-physics simulation and analysis capabilities deliver broader coverage across photonics, electrical and thermal domains. COUPE design enablement includes optical path simulation via Ansys Zemax OpticStudio®, photonic device simulation with Ansys Lumerical™, electromagnetic extraction through HFSS-IC Pro, and electro-thermal co-simulation using RedHawk-SC Electrothermal. These tools work in tandem to support the design of co-packaged optics solutions required for high-bandwidth data center interconnections.
Boosting Design Productivity and Shortening Development Cycles
Synopsys is collaborating with TSMC on the A14 process to introduce agentic run assistance within Synopsys Fusion Compiler™ built on the NanoFlex™ Pro architecture. The intelligent agent identifies timing optimization opportunities across different design flow stages to deliver superior design quality. In addition, AI-powered physical verification capabilities in Synopsys IC Validator™ continue to advance, accelerating the identification and resolution of Design Rule Check (DRC) violations and speeding up design closure for tapeout readiness.
Expanded IP Portfolio Covering Advanced Processes, AI, Edge Computing and Automotive Applications
Synopsys has achieved multiple key innovations in its IP portfolio this year, further solidifying its leadership in high-speed interconnects for AI, data center, edge computing and automotive markets. Through a key photonics collaboration, Synopsys launched a 224G IP solution supporting co-packaged optical Ethernet and UALink, meeting bandwidth demands for next-generation opto-electronic systems.
Meanwhile, Synopsys secured multiple first-silicon milestones on TSMC’s N5, N3P and N2P processes, including PCIe 7.0, HBM4, 224G, DDR5 MRDIMM Gen2, LPDDR6/5X/5, UCIe 64G and M-PHY v6.0 IP, setting new industry benchmarks in performance, energy efficiency and scalability.
Synopsys has further expanded its industry-leading, silicon-proven Foundation IP portfolio for TSMC’s N3P and N2P processes, offering embedded memory, standard cell libraries and I/O solutions to support low-power data centers, AI accelerators, mobile networks and advanced cloud computing platforms. With strong market adoption, industry-leading PPA performance, and a clear roadmap covering compact “C” nodes from N6 to N3, Synopsys Foundation IP is well-positioned to underpin the next wave of semiconductor innovation.
Furthermore, Synopsys strengthened its automotive leadership by launching a complete UCIe IP ASIL-B solution on the N5A process. Complementing its robust portfolio of high-reliability interface and Foundation IP on TSMC’s N5A and N3A nodes, the offering targets next-generation automotive SoCs and reinforces its momentum in the fast-growing automotive chiplet ecosystem.
(Reprinted from https://news.eccn.com/）