According to media reports, ChangXin Memory Technologies (CXMT) has officially launched risk‑based trial‑production of HBM3E memory, marking a crucial step in its foray into the high‑end high‑bandwidth memory segment.
CXMT is now ramping up its production capacity. It is projected that its monthly DRAM wafer output will reach 350,000 wafers by the end of this year, with continuous capacity expansion planned over the next few years to meet the growing demand from artificial intelligence and high‑performance computing applications.
At present, CXMT’s HBM3E production volume remains relatively limited, indicating that the technology is still in the early phase of risk‑based trial‑production, and a certain period will be required before large‑scale volume shipment.
Under JEDEC specifications, HBM3E features a 1024‑bit bus width, with a per‑pin data rate ranging from 9.2 Gbps to 12.4 Gbps. At the typical data rate of 9.6 Gbps, it can deliver a total bandwidth of up to 1.2 TB/s.
In terms of stacking configurations, an 8‑stack layer delivers a single‑stack capacity of 24 GB, while a 12‑layer stack reaches 36 GB, delivering high‑bandwidth, high‑capacity memory support for AI accelerators and data centres.
Considering CXMT’s previous track‑record of fast transition from risk‑based trial‑production to mass‑production, the market widely expects its HBM3E product to enter large‑scale mass‑production within weeks.
Furthermore, CXMT has demonstrated notable efficiency advantages in fab clean‑room construction: it takes only 12 months to complete a clean‑room project, compared with the industry‑standard cycle of two years for its peers. This capability provides solid support for subsequent capacity expansion and yield improvement.
(Reprinted from https://news.eccn.com/）